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Engineered Together—IBM Java and zEC12 Boost Workload Performance


IBM continues to invest aggressively in its Java technology on the System z mainframe. An important and notable element of this investment has been the ongoing vertical integration of the IBM JVM on System z. The new zEnterprise EC12 (zEC12) hardware design continues this trend.

With a second-generation, out-of-order pipeline, industry-leading cache design, and an ultra high-frequency (5.5 Ghz) core, the zEC12 boosts the performance of Java workloads. Beyond the enhanced chip design, zEC12 also brings innovative architectural features to market. These include:

  • Transactional execution
  • Runtime instrumentation
  • Pageable 1-Meg large pages using Flash Express
  • New instructions for improved branch prediction
  • 2GB fixed, large pages, and
  • A set of new trap instructions

IBM SDK7 for z/OS Service Refresh3 (IBM Java 7 SR3) on System z provides deep exploitation of the enhanced core and many of the new features available on zEC12. The combined performance uplift provided by the new core design and JVM offers an aggregate 60 percent improvement to IBM’s multi-threaded benchmark. This continues a trend across three generations of the hardware and IBM JVM, with the release-to-release improvements aggregating to 12 times the performance.

Optimization and Exploitation

The –Xaggressive command-line option in IBM Java 7 SR3 enables a variety of new optimizations and zEC12 exploitations in the IBM Testarossa Just-In-Time Compiler. These include the use of:

  • A new set of compare-and-trap instructions for reducing the overhead of implicit array bounds checks
  • Branch pre-load facility to mitigate the cost of expensive branches
  • More aggressive prefetching to mitigate the effects of data cache misses
  • Improved array initialization
  • Path-length reductions
  • Improvements to inlining and block reordering for better i-cache utilization, and
  • General instruction sequence tuning to reduce path-length and exploit the new pipeline more efficiently

Looking ahead, workloads will continue to scale out aggressively as thread counts explode on modern processors, and application storage footprints will grow to meet the needs of low-latency processing and big data. Therefore, the availability of functions like transactional memory and pageable large pages is expected to become critical to the evolution of the platform. As a lead exploiter of these technologies, IBM JVM is well positioned for these anticipated trends. With this in mind, let’s take a detailed look into these two features.

Clark Goodrich is a senior software engineer in the IBM Systems and Technology Group, System z performance organization working on the Java compiler. He has been with IBM since 1978 and holds four IBM patents. Prior to joining IBM, he did real-time programming at NASA's Goddard Space Flight Center for the Space Shuttle.

Jerry Zheng is a staff software developer in Java Just-in-Time Compiler development who is leading the effort of supporting transactional memory in IBM J9 JVM. He joined IBM in 2008 and has been working on exploiting new System z hardware features in a dynamic compiler.

Marcel Mitran is a senior technical staff member with IBM’s compiler team. He’s the lead architect for Java on System z, and has spent more than a decade developing dynamic and static compilation technology for System z.


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